Email Required, but never shown. By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of service , privacy policy and cookie policy , and that your continued use of the website is subject to these policies. By using our site, you acknowledge that you have read and understand our Cookie Policy , Privacy Policy , and our Terms of Service. Itamar FPGA 1 1. Pins can cause a whole slew of issues if they are not mapped right on this core.

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Sign up using Facebook. Power is usually less of problem on devkits if you have already run the demo that came with the kit.

Linux source code: drivers/net/ethernet/altera/altera_tse_main.c (v) – Bootlin

Sign up or log in Sign up using Google. Rich Maes 6 If you haven’t simulated, you really should.

Similarly, if you may want to bring out your reset to a pin altsra check it. It should define a pin for reset, input clock and signal standards. No activity on the interface is kind of clue. Stack Overflow works best with JavaScript enabled. If it’s not working in SIM, why would it ever work in real life.

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xltera Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies. Make sure you are using the QIP file to synthesize the design. It’s not clear to me if you are just simulating or synthesizing. Then, using System Console, I am configuring the Triple Speed Ethernet core as described in the core’s user guide link here at section Register Initialization and instruct the packet generator module also using System Console to start and generate Ethernet packets into the TSE core’s transmit Avalon-ST sink interface ports.

This doesn’t seem like your issue to me because you say the GMII is flat lined.

By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies. By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service.

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It will automatically include your auto generated SDC constraints.

Starting the basic checks, Have you simulated it? Sign up using Email and Password.

Altera TSE: Change driver name used by Ethtool [Linux 3.15]

You will tde need to add your own PIN constraints, more on that later. Pins can cause a whole slew of issues if they are not mapped right on this core.

Alot of times, this goes in the. One way to check, is to route your clocks to spare pins and o-scope them and insure they are what you think they are. I’ll assume you are leveraging something from Terasic. Itamar FPGA 1 1.

netdev – [PATCH RFC 3/3] Altera TSE: Add Altera Triple Speed Ethernet (TSE) Driver

Can any one please, please help me with this? Email Required, but never shown. Post as a guest Name.

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